The present invention relates to a booster circuit and a semiconductor memory device having the same, and more particularly to a booster circuit used in a non-volatile semiconductor memory device such as an EEPROM.
FIG. 1 shows an example of a conventional booster circuit. FIG. 2 shows waveforms of clock pulse signals .phi. and /.phi. (the mark of "/" means that the signal is inverted).
The booster circuit shown in FIG. 1 includes, for example, four n-channel MOS transistors 1 to 4 and three capacitors 5 to 7. An end of a current path of the transistor 1 and a gate thereof are supplied with a power supply voltage Vcc. The other end of the current path of the transistor 1 is connected to an end of a current path of the transistor 2 and a gate thereof, as well as an end of a capacitor 5. The other end of the capacitor 5 is supplied with a signal .phi.. The other end of the current path of the transistor 2 is connected with an end of a current path of the transistor 3 and a gate thereof, as well as an end of the capacitor 6. The other end of the capacitor 6 is supplied with a signal /.phi.. The other end of the current path of the transistor 3 is connected with an end of a current path of the transistor 4 and a gate thereof, as well as an end of the capacitor 7. The other end of the capacitor 7 is supplied with a signal .phi.. The other end of the current path of the transistor 4 outputs a boosted voltage Vout.
The clock pulse signal .phi. and the inverted signal/.phi. thereof oscillate, for example, between the power supply voltage Vcc and 0V as a ground potential as shown in FIG. 2. The clock signals .phi. and /.phi. have a frequency expressed as f.
Each of the n-channel MOS transistors 1 to 4 has a threshold value expressed as Vt. The capacitors 5, 6, and 7 have an equal capacity C. Further, the number of stages of the booster circuit is expressed as N and indicates the number of the capacitors of the booster circuit. In the booster circuit shown in FIG. 1, N is 3.
FIG. 3 shows a circuit equivalent to the booster circuit shown in FIG. 1. The negative electrode of the voltage source 8 is grounded, and the positive electrode of the voltage source 8 is connected to an end of a resistor 9. The other end of the resistor 9 outputs a voltage Vout. The current flowing through the resistor 9 is expressed as Iout. An output voltage E of the voltage source 8 is obtained by (N+1).times.(Vcc-Vt). A resistance value R of the resistor 9 is obtained by 1/(c.times.f).
FIG. 4 shows a relationship between the output voltage Vout and the output current Iout.
In order to increase the output current Iout without changing the frequency f and the capacity C of each capacitor, the pentode threshold value Vt of the MOS transistors 1 to 4 needs to be 0. For example, the threshold value Vt can be substantially set to 0 by using an intrinsic n-channel MOS transistor, such as an n-channel MOS transistor which is formed on a p-type substrate and has a channel region not implanted with channel ions.
FIG. 5 shows a circuit in which a conventional booster circuit is added with a circuit for detecting an output voltage of the booster circuit to control the booster circuit.
In FIG. 5, the booster circuit 11 is the same as that shown in FIG. 1, and also, a power supply voltage Vcc and clock pulse signals .phi. and /.phi. are supplied while a boosted voltage Vcp is outputted. The output voltage Vcp is used, for example, as an internal power supply voltage of a semiconductor integrated circuit.
The boosted voltage Vcp is supplied to an end of a resistor 12, and the other end of the resistor 12 is connected to an end of a resistor 13. The other end of the resistor 13 is grounded. The resistance values of the resistors 12 and 13 are respectively expressed as R1 and R2.
An inverted input terminal of an operational amplifier 14 is connected to a connection point between the resistors 12 and 13. The voltage at the connection point is expressed as Vg. The inverted input terminal of the operational amplifier 14 is supplied with a reference voltage Vref. The operational amplifier 14 outputs an oscillator enable signal OSCE.
A ring oscillator 15 generates and outputs clock pulse signals .phi. and /.phi. in response to a signal OSCE.
In the circuit shown in FIG. 1, for example, the gate of the n-channel MOS transistor 1 and a first terminal of the current path is applied with a power supply voltage Vcc. The voltage at a second terminal of the current path of the transistor 1 is boosted to be higher than the power supply voltage Vcc. In this case, since the transistor 1 is turned off, no current must flow back to the first terminal from the second terminal of the current path.
However, if the MOS transistor 1 is of an intrinsic type, the threshold value Vt, for example, about -0.1 V which is lower than that obtained in case of using an ordinary n-channel MOS transistor. Therefore, while a voltage vcc is applied to the gate of the transistor 1, a slight current flows through the transistor 1, thus causing a back flow of current in a direction from a boosted voltage to a power supply voltage. Further, if the back gate voltage of the transistor 1 is small or the power supply voltage Vcc is low, the back flow is more apparent.
Also, if the transistor operates in an environment of a high temperature, the threshold voltage Vt decreases to satisfy a relation of Vt&lt;0. Therefore, a back flow as described above is caused too.
Also, if the transistor is of an enhancement type, the threshold value decreases due to downsizing of the transistor if the transistor, and a back flow is caused too.
Thus, if a transistor having a low threshold value Vt is used, a leakage current from the output side to the input power voltage Vcc side is always caused due to its back gate effect or a temperature influence, so that the operating current is increased.
Consideration is then taken into a case in which the power supply voltage Vcc is higher than the output voltage Vcp of the booster circuit in the circuit shown in FIG. 5. In FIG. 6, a line 16 represents a load characteristic of the booster circuit in the case, i.e., a relationship between the output voltage and the output current of the booster circuit 11. Another line 17 represents a relationship between a voltage applied between both ends of the resistors 12 and 13 connected in series, and a current flowing through the resistors 12 and 13. The voltage at the cross point of the lines 16 and 17 is the output voltage Vcp of the booster circuit 11. The number of capacitors in the booster circuit 11 is expressed as N, and the threshold value of the MOS transistors constituting the booster circuit 11 is expressed as Vt. A desired power supply voltage is [(R1+R2)/R2].times.Vref.
Where a relation of Vcc-(N+1).times.Vt&gt;[(R1+R2)/R2].times.Vref is satisfied, the booster circuit 11 does not perform boosting but outputs a voltage obtained by reducing the power supply voltage Vcc, as an internal power supply voltage.
From a relation of [R2/(R1+R2)].times.[Vcc-(N+1).times.Vt](=Vg)&gt;Vref, the output signal OSCE of the operational amplifier 14 is of a low level. Therefore, the ring oscillator 15 does not operate, and each of the signals .phi. and /.phi. is kept at a low or high level.
Consequently, the output voltage Vcp is higher than the desired level [(R1+R2)/R2]&gt;.times.Vref. The difference between the output voltage and the desired voltage level increases as an external power supply voltage Vcc increases, as can be seen from FIG. 6.
If the external power supply voltage Vcc is allowed to exceed a standard voltage of 3 V and increase to, for example, 5 V, the internal power supply voltage increases in accordance with the external power supply voltage Vcc. Then, a problem occurs in the reliability of peripheral elements and memory cells. Like in the booster circuit shown in FIG. 1, a problem occurs in that a current flows back to the power supply voltage in the booster circuit in an operation environment of a high temperature. Further, if the threshold voltage decreases due to the same factors as those in the case of the booster circuit shown in FIG. 1, the internal power supply voltage Vcp increases, thereby affecting the reliability of peripheral elements and memory cells.